Better than FPGA

Better than FPGA

Multi-core heterogeneous compute platform

Xilinx announced a new product category called adaptive compute acceleration platform (ACAP) that goes far beyond the capabilities of an FPGA. An ACAP is a highly integrated multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. Its adaptability delivers performance per-watt that is unmatched by CPUs or GPUs.

Everest is expected to achieve 20x performance improvement on deep neural networks compared to today?s latest 16nm Virtex VU9P FPGA. (Bild: Xilinx Ltd)

Everest is expected to achieve 20x performance improvement on deep neural networks compared to today’s latest 16nm Virtex VU9P FPGA. (Bild: Xilinx Ltd)

An ACAP is ideally suited to accelerate a broad set of applications in the emerging era of big data and artificial intelligence, e.g. video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. The first ACAP product family, codenamed Everest, will be developed in TSMC 7nm process technology. An ACAP has – at its core – a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). An ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory depending on the device variant. Software developers will be able to target ACAP-based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools. Everest is expected to achieve 20x performance improvement on deep neural networks compared to today’s latest 16nm Virtex VU9P FPGA. ACAP has been under development for four years at an accumulated R&D investment of over one billion US-dollars. There are currently more than 1,500 hardware and software engineers designing ACAP and Everest. Software tools have been delivered to key customers. Everest will tape out in 2018 with customer shipments in 2019.

Thematik: inVISION 3 2018
Ausgabe:
Xilinx Ltd
www.xilinx.com

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