New Cables and Two Cores in Parallel for Camera Link HS
The initial Camera Link HS standard was ratified in 2012 and it was updated to version 1.1 a couple of years ago – everything was kept the same, but it allowed for higher speeds on the connectors. The aim was to leverage the standard to take advantage of those higher speeds and get everything into one fiber.
Picture 1 | 14G will be in the next CLHS release enabling 11.4GBytes/sec in a single cable. Alysium is supporting the active optical cable and is soon to release their second generation which shrinks the connector that houses the optical engine. (Bild: Teledyne Dalsa Inc.)
CLHS built on the key strengths of Camera Link and added bi-directional GPIO and new triggering capabilities to meet customers‘ demands. Another CLHS goal is to allow on-the-fly changing of Window ROIs. And so, we came up with a remote DMA style of packet, which allows the frame grabber to know which pixels are included in each packet and therefore perform image preprocessing on the fly.
Active Optical Cables
High bandwidth cameras need many data lanes to transfer data from camera to frame grabber. So CLHS has a seven down, one up lane cable. Teledyne Dalsa currently uses each lane at 10G, which gives 1.2gigabytes/sec of uplink and 8.4gigabytes/sec of effective data bandwidth returned to the frame grabber. Rev 1.1 allowed 12.5G per lane on this cable, pushing the effective bandwidth to 10.2Gbytes/sec. This is still not enough bandwidth for upcoming products, and so 14G will be in the next CLHS release enabling 11.4GBytes/sec of throughput. Alysium and Hewtech have been supporting the active optical cable (AOC) and Alysium is soon to release their second generation which shrinks the connector that houses the optical engine and still maintains the 1W of power dissipation. Another change that has been discussed in the committee, is to allow CLHS to use 25Gbps optical technology. Studies confirm the current IP core available from the AIA is able to run at the required speed without change, and so the migration to the new speed will happen when the optical engines and the supporting FPGAs become cost effective.
Two Existing Cores in Parallel
CLHS leverages widely available ethernet technology. Ethernet is also going to 50Gbps per lane, and there are FPGAs out there that can support 50Gbps capability. So, one proposal in the committee is to parallel two CLHS cores, as they are today, put in extra little bit of logic to, concatenate those two cores into one. And then at the receiver end, split a concatenated signal into two receive signals. So, that’s a very simple change. But it’s a long way off. However, it’s good to know that we can keep reusing the core technology for many years to come without change, because it works.
