Expertenrunde: Wie geht es bei den Highspeed-Interfaces weiter?

CLHS: Preparing for 50G and beyond

Autor: Martin Schwarzbauer, Product Development, PCO AG

The Camera Link HS working group has already begun designing a solution for 50G and beyond.

The need for high-speed interfaces increases dramatically. 10G Ethernet becomes the standard for consumer hardware, 25G is easily available for the industry, and 100G and beyond is already common practice for servers. Also, CoaXPress (CXP) changed from copper to fiber cable to handle high-speed data rates beyond 10/12.5G due to the limits of the electrical phy. Camera Link HS (CLHS) is in the final stage for specifying 25G with a MPO connector that will enable bandwidths of 100G (4x 25G) with a single connector. On top of that, a bandwidth of 175G is possible when using a CX4 connector. While the speed increases, the X-Protocol remains completely unchanged.The well-designed CLHS Committee IP-Core distributed by ‘The Association For Advancing Automation – Vision & Imaging’ is ready for 25G without any modification for FPGA with a 25G capable transceiver. This very low-cost IP-Core is well tested with many FPGAs from Xilinx, Intel, Lattice, and MicroSemi. Additionally, it can be used with other bitrates to address low-cost FPGAs with a 16G transceiver. With the power of the forward error correction (FEC) and the efficient protocol fitted for 64b/66b coding, the effective bandwidth clearly surpasses the bandwidth from other technologies like Ethernet and CXP. Especially with small regions of interest, the optimized protocol results in a very effective transmission. The Camera Link HS working group has already begun designing a solution for 50G and beyond. The focus is on how to extend the protocol for future speeds with minor influences on the currently well-tested IP-Core and protocol. The idea, however of using a bridge protocol to get access for faster speeds is not considered. While on the one hand there might be the advantage loss of the optimized protocol used for 64b/66b, the downside of this approach is that there must always be a time-consuming rework of the IP-core because of the need of a wider internal interface. Therefore, the concept of virtual channels has been introduced, using several CLHS links over a single lane. This only requires slight changes in the IP-Core. The impact on the standard is also very small. With the extension to CLHS, the standard gets ready for the future to benefit from any new hardware technology for high-speed interfaces.

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